1. Field of the Invention
The present invention relates generally to semiconductor apparatus and manufacturing methods thereof and, more particularly, to a technique for formation of a desired conductive interconnection pattern without being affected by step-like portions formed in an interlayer insulation film.
2. Description of the Background Art
Mostly, an integrated circuit (hereinafter referred to as "IC") memory such as a DRAM (Dynamic Random Access Memory) is comprised of a memory cell array including a large number of storage elements and a peripheral circuit necessary for input/output, and the memory cell array and the peripheral circuit are formed on the same substrate.
FIG. 12 is a block diagram showing one example of structure of a general DRAM. With reference to FIG. 12, a memory cell array 1 includes a plurality of word lines and a plurality of bit lines arranged to cross over each other therein. Memory cells are provided at respective cross-over points of the word lines and the bit lines. Each of the memory cells is selected by selecting a corresponding one of the word lines by an X address buffer decoder 2 and a corresponding one of the bit lines by a Y address buffer decoder 3. Data is written into a selected one of the memory cells, or data stored in the selected memory cell is read. Instruction of such data writing/reading is made by a read/write control signal (R/W) which can be applied by a R/W control circuit 4. In data writing, input data (Din) is applied as an input to the selected memory cell via R/W control circuit 4. In data reading, data stored in the selected memory cell is detected and then amplified by a sense amplifier 5. The amplified data is output as output data (Dout) via a data output buffer 6 to the outside.
FIG. 13 is an equivalent circuit diagram of a dynamic type memory cell for use in explaining a writing/reading operation of the memory cell.
Referring to FIG. 13, the dynamic type memory cell includes a set of field effect transistor 7 and capacitor 8. A gate electrode of field effect transistor 7 is connected to a word line 9. A source/drain electrode of field effect transistor 7 connected to capacitor 8 is connected to a bit line 10. A predetermined potential is applied to word line 9 in data writing. This renders field effect transistor 7 conductive, so that charges applied to bit line 10 are stored in capacitor 8. In data reading, a predetermined potential is applied to word line 9. This renders transistor 7 conductive, so that the charges stored in capacitor 8 are extracted via bit line 10.
A description will now be made on one example of structure of a conventional IC memory with reference to FIGS. 11A and 11B. FIG. 11A is a cross-sectional view showing a part of a conventional memory cell array 102 and peripheral circuitry 101, and FIG. 11B is a plan lay-out of the corresponding part. Here, a stacked capacitor is shown as an example of a capacitor of a memory cell.
In this memory cell, with reference to FIGS. 11A and 11B, a field effect transistor 18 is formed on a silicon substrate 11. Field effect transistor 18 includes a gate oxide film 19, a gate electrode 20, an overlying insulator film 21 and a sidewall insulator film 22. While gate electrode 20 is not shown in the figures due to structure of the memory cell array, the gate electrode is disposed also on a field oxide film 12 for isolation. A diffusion layer 13 for reinforcing isolation is formed beneath field oxide film 12. Also, diffusion layers 14 and 15 serving as a source/drain region of field effect transistor 18 are formed.
As the one corresponding to capacitor 8 of FIG. 13, a capacitor including a storage node 29, a capacitor insulation film 31 and a cell plate 32 is formed. This capacitor is electrically connected through a contract hole 27 to the aforementioned diffusion layer 15. As the one corresponding to bit line 10 of FIG. 13, a bit line 40 is formed. This bit line 40 now has polycide structure formed of a polycrystalline silicon layer 38 and a tungsten silicide layer 39. This bit line 40 is electrically connected through a contact hole 34 to the aforementioned diffusion layer 14. A diffusion layer 17 is formed in a peripheral circuit 102 and electrically connected through a contact hole 37 to bit line 40. Insulation between the capacitor and bit line 40 is achieved by an interlayer insulation film 33.
At present, IC memories employ the above-described stacked capacitors in order to increase integration density and capacitance. Thus, there arises a problem with respect to step-like portions due to a difference in height between a portion on an IC chip where a capacitor is disposed and a portion where no capacitor is disposed. Particularly, in a case where bit line 40 is formed in an upper portion of the capacitor as shown in the foregoing conventional example, if depth of focus in resist pattern formation is smaller than the above-described step-like portions in photolithography using a photoresist mask for use in formation of bit line 40, it has been very difficult to precisely process all bit lines 40 on chip to a desired dimension in comply with the photoresist mask.